1. Field
Exemplary embodiments of the present invention relate to an e-fuse array circuit, and more particularly, to a technology for improving a programming method of an e-fuse array circuit.
2. Description of the Related Art
A general fuse recognizes a data based on whether the fuse is cut by a laser or not. Therefore, it is possible to set a fuse in the stage of wafer, but after the wafer is mounted on a package, the fuse cannot be programmed.
To overcome the drawback, an e-fuse is used. The e-fuse stores a data by using a transistor and changing the resistance between a gate and a drain/source of the transistor.
FIG. 1 illustrates an e-fuse including a transistor, where the e-fuse operates as either a resistor or a capacitor.
Referring to FIG. 1, the e-fuse includes a transistor T, and a power source voltage is supplied to a gate G while a ground voltage is supplied to a drain/source D/S.
If a power source voltage of an ordinary level that the transistor T may tolerate is applied to the gate G, then the e-fuse may operate as a capacitor C. Therefore, no current flows between the gate G and the drain D or the source S. However, if a high voltage that the transistor T may not tolerate is applied to the gate G, then the gate oxide of the transistor T is destroyed to short the gate G and the drain source D/S. As a result, the e-fuse may operate as a resistor R. Therefore, current flows between the gate G and the drain/source D/S.
Based on these results, the data of the e-fuse is recognized from the resistance value between the gate G and the drain/source D/S. The data of the e-fuse may be recognized by (1) enlarging the size of the transistor T, or (2) using an amplifier, instead of increasing the size of the transistor T, and sensing the current flowing through the transistor T. If the transistor T is enlarged, the data of the e-fuse may be recognized without performing a sensing operation. The above two methods, however, have concerns regarding dimensional restrictions because the transistor T that constitutes the e-fuse has to be enlarged or each e-fuse has to be equipped with an amplifier for amplifying data.
U.S. Pat. No. 7,269,047 discloses a technology for forming an e-fuse in a type of an e-fuse array in order to reduce the area occupied by the e-fuse.
FIG. 2 is a block view illustrating a conventional cell array 200 formed of e-fuses.
Referring to FIG. 2, the cell array 200 includes memory cells 201 to 216 arrayed in N rows and M columns. The memory cells 201 to 216 include memories M1 to M16 and switches S1 to S16, respectively. The memories M1 to M16 are e-fuses having the characteristics of resistors or capacitors based on whether they are ruptured or not. In other words, the memories M1 to M16 may be regarded as resistive memories that store data based on the intensity of resistance. The switches S1 to S16 may electrically connect the memories M1 to M16 with column lines BL1 to BLM under the control of row lines WLR1 to WLRN.
Hereafter, it is assumed that a second row is a selected row, and a Mth column is a selected column, in other words, it is assumed that a memory cell 208 is a selected memory cell. The voltage supplied to the selected memory cell 208 and the voltage supplied to unselected memory cells 201 to 207 and 209 to 216 during a program and read operation are described below.
Program Operation
The selected row line WLR2 is enabled and the other row lines WLR1 and WLR3 to WLRN of the selected row are disabled. Therefore, switches S5 to S8 are turned on, and the other switches S1 to S4 and S9 to S16 are turned off. A high voltage (a rupture voltage) that could destroy the gate oxide of an e-fuse, which is generally generated by pumping a power source voltage, is supplied to the program/read line WLP2 of the selected row, and a low voltage, e.g., a ground voltage, is supplied to the other program/read lines WLP1 and WLP3 to WLPN. The selected column line BLM is coupled with a data access circuit, and unselected column lines BL1 to BLM-1 float. If an input data is a program data, e.g., ‘1’, then the data access circuit drives the selected column line BLM to a low-level voltage to program (or rupture) the memory M8 of the selected memory cell 208. If the input data is not a program data, e.g., ‘0’, the data access circuit drives the selected column line BLM to a high-level voltage so that the memory M8 of the selected memory cell 208 may not be programmed. Because the unselected column lines BL1 to BLM-1 float, the memories M5 to M7 may not be programmed even though a high voltage is applied to the gates.
Read Operation
The selected row line WLR2 is enabled, and the other row lines WLR1 and WLR3 to WLRN of the selected row are disabled. Therefore, the switches S5 to S8 are turned on, and the other switches S1 to S4 and S9 to S16 are turned off. A voltage, which is generally a power source voltage, is supplied to the program/read line WLP2 of the selected row, while a low voltage, e.g., a ground voltage, is supplied to the other program/read lines WLP1 and WLP3 to WLPN. The selected column line BLM is coupled with a data access circuit, and the unselected column lines BL1 to BLM−1 float. If current flows through the selected column line BLM, then the data access circuit may recognize that the memory M8 is programmed. In other words, the data access circuit may recognize that the data of the memory 208 as ‘1’. If current does not flow through the selected column line BLM, then the data access circuit may recognize that the memory M8 is not programmed. In other words, the data access circuit may recognize that the data of the memory 208 as ‘0’.
Although it is illustrated in the above that one column line BLN is selected among the column lines BL1 to BLN, a plurality of column lines may be selected at one time. In short, a plurality of memory cells belonging to the same row may be simultaneously programmed or read.
FIG. 3 is a block view illustrating a conventional e-fuse array circuit including the cell array 200 of FIG. 2.
Referring to FIG. 3, the e-fuse array circuit includes the cell array 200 shown in FIG. 2, a row circuit 310, a column decoding circuit 320, and a data access circuit 330.
The row circuit 310 controls row lines WLR1 to WLRN and program/read lines WLP to WLPN for the program operation and the read operation that are described above. A row address ROW_ADD inputted to the row circuit 310 designates a row that is selected among a plurality of rows, and a program/read signal PG/RD indicates a program operation or a read operation.
The column decoding circuit 320 electrically connects a column line selected based on a column address COL_ADD among column lines BL1 to BLM with the data access circuit 330. The drawing exemplarily illustrates four column lines <0>, <1>, <2>, and <3> selected among the column lines BL1 to BLM.
The data access circuit 330 controls the access of data of the column lines that are selected by the column decoding circuit 320. During a program operation, the data access circuit 330 controls the selected column lines to be programmed or not to be programmed based on an input data DI<0:3>. During a read operation, the data access circuit 330 senses whether current flows through the selected column lines or not, and it outputs the sensing result as an output data DO<0:3>.
The e-fuse array circuit may store data by destroying or not destroying the gate oxide of a transistor that constitutes an e-fuse. The gate oxide may be or may not be easily destroyed based on the characteristics of the transistor. In short, a resistive memory device may have a failure based on the characteristics of the transistor. Therefore, it is required to develop a technology that improves the reliability of a program operation of an e-fuse array circuit.